Low Power Design of Sr Flip Flop Using 45nm Technology

This paper illustrates the design of low-power, high-performance SR flip-flop. The speedy technical trends are engrossing to decrease the geometrical feature size and power consumption of the integrated circuit in VLSI designs. The proposed design shows the comparison with conventional CMOS circuit on the basis of power consumption and propagation delay and can save up to a significant amount of the power and speed. Therefore proposed design is more optimized than the conventional CMOS design because the efforts have done to use the minimum power during schematic designing. The circuits are simulated at transistor level using Cadence Virtuoso Tool at 45 nm process technology.